1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, an evaluation method of a semiconductor device, and a semiconductor device.
2. Description of the Related Art
Among semiconductor devices such as an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) is a trench gate semiconductor device having a metal oxide semiconductor (MOS) gate structure in a trench. A trench gate semiconductor device has many trench MOS cells disposed on a semiconductor substrate at predetermined intervals, each having a MOS gate structure formed in a trench to form a channel region (an inversion layer) in a trench side wall.
Each of the trench MOS cells disposed on the semiconductor substrate is usually at a gate potential. When all of the trench MOS cells operate concurrently, however, a problem arises in that an excessive flow of saturated current causes a parasitic thyristor to latch up and an effective parasitic capacitance Qg to increase, whereby switching loss increases. Thus, a device has been proposed that is configured to have the trench MOS cells not densely disposed therein by reducing (culling) the number of trench MOS cells, whereby the interval between adjacent trench MOS cells is increased. When the trench MOS cells are culled, however, a problem arises in that the electric field concentration increases at the bottom portion of the trench and the breakdown voltage of the element decreases.
As a device to solve the problems above, a device has been proposed which trench MOS cells that form no channel region in the trench side wall (hereinafter, respectively referred to as a “dummy trench MOS cell”) are disposed therein in addition to the trench MOS cells that are at the gate potential, and a dummy gate electrode constituting the dummy trench MOS cell is short-circuited (shorted) to an emitter electrode. The number of trench MOS cells each at the gate potential can be reduced by disposing the dummy trench MOS cells that are at the emitter potential without culling the trench MOS cells. Thus, increases in the effective parasitic capacitance Qg can be prevented and the electric potential concentration at the bottom portion of the trench can be alleviated.
In the fabrication process of the trench gate semiconductor device, usually, during wafer inspection after the wafer process, screening is executed to evaluate the reliability of the gate insulator film by applying a predetermined voltage to the gate insulator film of the trench side wall by applying a voltage between the gate electrode in the trench and a semiconductor portion sandwiched between the trenches. No potential difference is, however, generated between a dummy gate electrode and the semiconductor portion sandwiched between the trenches because the dummy gate electrode constituting the dummy trench MOS cell is at a potential other than the gate potential (for example, the emitter potential). Therefore, in a conventional screening, no voltage can be applied to the dummy gate insulator film constituting the dummy trench MOS cell and consequently, the reliability of the dummy gate insulator film cannot be measured.
As a screening method for evaluating the reliability of the dummy gate insulator film constituting the dummy trench MOS cell, a method has been proposed according to which the dummy gate electrode constituting the dummy trench MOS cell is connected to a dummy gate pad, a DC power source is connected between an emitter pad and a dummy gate pad during the wafer inspection after the wafer process, and thereby, voltage is applied to the dummy gate insulator film (see, for example, Japanese Laid-open Publication No. 2013-251466).
The following method has been proposed as another screening method. An outer peripheral region disposed around a cell region is used as a region to run the wires of an IGBT element and a diode element. This outer peripheral region has plural pads disposed thereon to which the active regions respectively between the trenches are connected and that electrically connect the gate electrode and the trench electrode to the exterior. The gate electrodes and the trench electrodes are each electrically connected to the pads (see, for example, Japanese Laid-open Publication No. 2011-243695 (paragraphs 0034 to 0036)).
The following method has been proposed as yet another screening method. A first floating wiring is formed in a two-layer structure such that in the lower layer portion, portions are distant from each other by a predetermined interval (portions such as a portion electrically connected to doped Poly-Si that leads to the dummy gate electrode, and a portion electrically connected to a first floating layer). The screening inspection step is executed prior to the formation of the upper layer portion (see, for example, Japanese Laid-open Publication No. 2010-050211).
According to Japanese Laid-open Publication Nos. 2013-251466 and 2011-243695, the dummy gate electrode and the exterior are configured to be electrically connected to each other and external parts are necessary such as, for example, a driver circuit to control the potential of the dummy gate electrode.
As a method of connecting predetermined electrodes to each other, a method has been proposed that includes a step of forming, among plural conductive patterns, one conductive pattern and other plural conductive patterns respectively disposed to be distant from the one conductive pattern and to sandwich the one conductive pattern, a step of coating at least the portion of the one conductive pattern sandwiched by the other conductive patterns with an insulating material, and a step of electrically connecting the other conductive patterns to each other above the points coated by the insulating material, by non-electrolytic plating (see, for example, Japanese Laid-open Publication No. 2006-186154).
As another method of connecting predetermined electrodes to each other, a method has been proposed that includes a step of forming for each device, a bridging point disposed linking each of the plural devices and configured by a metal pad adjacent to and distant from each of the devices to electrically isolate the devices, a step of distinguishing faulty devices and acceptable devices from each other by individually testing the devices and measuring the functionality of each of the devices in terms of predetermined operation parameters, a step of preventing solder leakage by coating the bridging points of the faulty devices by a coating fluid, and a step of electrically isolating the faulty devices by applying solder to the devices overall to bridge adjacent and distant metal pads by solder and thereby, electrically connect the bridging points of the acceptable devices (see, for example, Japanese Laid-open Publication No. H2-010855).
With Japanese Laid-open Publication No. 2010-050211, however, fine processing for metal wires is necessary to form the structure in which portions are separated by the predetermined interval such as the portion electrically connected to the doped Poly-Si that leads to the dummy gate electrode and a portion electrically connected to the first floating layer, in the lower layer portion of the floating wiring (the metal wiring) in the active region and the runner wiring portion. Susceptible to the effects of process variability, the metal wires formed to be separated by the predetermined interval may be short-circuited to each other. The reliability of the dummy gate insulator film cannot be evaluated by the screening and a problem arises in that the failure rate of the product after the product is put in the market (hereinafter, referred to as “market failure rate”) increases.